Foundry, equipment and design tools

The layer that wins either way

The chips layer is a contest: Nvidia against AMD against the buyers’ own designs. This layer sits underneath the contest. Nearly all leading AI accelerators, Nvidia’s and the custom ones alike, are manufactured by TSMC, and most are packaged with its advanced packaging technology, which places the processor and its high-bandwidth memory side by side. TSMC buys its most critical lithography tools from one supplier, ASML. Every chip designer uses design software from Synopsys or Cadence.

That is why the layer’s numbers are a cleaner read of the build-out than any single chip company’s. TSMC reported $121B of revenue for 2025, +38%, at a 60% gross margin and a 51% operating margin. It describes high-performance computing, including AI, as its key growth driver. Its two largest customers accounted for 19% and 17% of its 2025 revenue, and its ten largest for 78%.

Equipment: the build-out of the build-out

The toolmakers grow when chipmakers add capacity, which makes them a leading indicator. ASML reported €32.7B of sales for 2025, +16%, with its largest customer accounting for 23.9%. Among the US-listed toolmakers, Lam Research, whose etch and deposition tools sell heavily to memory makers, grew +33% over its latest four quarters, while Applied Materials grew +8% and KLA +16%.

The fastest grower in the group was Teradyne, +58%: AI accelerators and HBM stacks are complex enough that testing them takes far more time and equipment than ordinary chips. Amkor, which packages and tests chips for others, grew +16% at a 17% gross margin. ASE, the largest company in that business, reported $20.6B of revenue for 2025, +13%, at a 18% gross margin, and spent $5.2B on capex that year. Outsourced packaging is a volume business, unlike the advanced packaging TSMC does itself, though both are now adding capacity for AI.

Spending on equipment is not only about AI. Phones, PCs, cars and industrial chips are a large share of demand, and export rules shape how much the toolmakers can sell to China. Over two years the US-listed companies in this layer grew revenue +37%, a fraction of the chip layer’s pace: AI is adding to their business rather than replacing it.

Design software: a toll on every chip

Synopsys and Cadence sell the software used to design chips, and both are deeply embedded in every chipmaker’s workflow. Synopsys grew +46% over its latest four quarters, partly because it acquired the simulation company Ansys; Cadence grew +18%. The rise of custom silicon is good for them: every hyperscaler that designs its own accelerator becomes a customer, and every new generation needs more design work.

Their revenue is small next to the hardware this page describes, but it is high-margin and recurring, and it rises with the number of chip designs rather than the number of chips shipped. That makes it one of the steadier ways the stack monetizes AI.

Concentration: the risk under everything

The same concentration that makes this layer powerful makes it the stack’s biggest single point of failure. Most leading-edge chips are made in Taiwan, the most advanced lithography tools come from one company in the Netherlands, and advanced packaging capacity has repeatedly been the constraint on how many accelerators can be shipped. TSMC is building factories in the United States, Japan and Germany, and Intel and Samsung are trying to offer alternatives, but for the accelerators that matter most today there is no near-term substitute.

For an investor, that cuts two ways. It gives TSMC and ASML pricing power and long visibility, which their margins reflect. It also means a disruption at one company, from geopolitics, an earthquake or export controls, would reach every other layer on the map. No filing can quantify that risk, but TSMC’s 20-F discusses it at length, and anyone holding AI stocks is exposed to it whether or not they own TSMC.

What the layer says about the cycle

Foundry and equipment orders are where the industry’s expectations show up first, because capacity takes two to three years to build. When TSMC raises its capital spending and the toolmakers report growing orders from leading-edge logic and memory, the industry is preparing for demand years ahead. When those orders flatten, the industry is telling you it has enough capacity for the demand it expects.

TSMC spent $40.6B on capital projects in 2025. Its capital spending plans, published with its quarterly results, are among the most useful single numbers for anyone trying to judge how long the AI build-out will run.

The companies, side by side

Latest four reported quarters for US filers; latest fiscal year for 20-F filers (marked). Underlined names have their own company page; the others link to the company’s filings on SEC EDGAR. Margins are left blank where a company doesn’t report gross profit or cost of revenue.

Where the money comes from and goes

This layer is paid by chips and memory and networking. Its own costs are mostly labor, materials, fuel and its own capital spending, outside the stack. For the dollar amounts and who keeps them, see following the money.

What to watch in the next filings

• TSMC’s monthly revenue reports and quarterly capex guidance.
• ASML’s orders, especially for its most advanced EUV tools.
• Advanced-packaging capacity: a constraint on accelerator supply through much of the build-out.
• Toolmakers’ sales to memory makers, the read on HBM capacity additions.
• Export rules affecting equipment sales to China.